000 00484nam a22001577a 4500
008 180224b xxu||||| |||| 00| 0 eng d
020 _a9788177589184
082 _a621.392
_bPAL
100 _aPalnitkar, Samir
245 _aVerilog HDL
_ba guide to design and synthesis IEEE 1364 - 2001 compliant
250 _a2nd
260 _aNew Delhi
_bPearson
_c2003
300 _a490p.
650 _aVerilog (Computer hardware description language)
_xDigital electronics
942 _2ddc
_cBK
_0277
999 _c4093
_d4093